1. Field of the Invention
The present invention relates to memory devices and, in particular, to an integrated circuit memory device architecture in which the column decoder select lines are used to create transfer bus segmentation, thereby reducing the capacitance seen by individual memory cells.
2. Discussion of the Prior Art
Speed and density are critical to successful semiconductor memory cell design. However, as memory density increases, bit line and transfer bus capacitances also increase, thereby slowing down cell access time. To improve cell access time, memory arrays are typically divided into segments to reduce the above-mentioned capacitances.
FIG. 1 shows a single row 100 of a typical static random access memory (SRAM) array that includes a matrix of rows and columns of memory cells. Those skilled in the art will appreciate that both the number of SRAM cells in an individual row of the array and the total number of rows in the array can vary widely. The illustrated row 100 includes sixteen individual conventional SRAM cells of the type shown in FIG. 2.
The FIG. 2 SRAM cell includes two cross-coupled field effect transistors connected between supply and ground via respective resistive loads to define complementary output nodes A and A. Nodes A and A may be accessed for read and write operations by turning on the cell's internal pass gate transistors via the word line associated with the cell, thereby connecting nodes A and A to the complementary cell bit lines BL and BL, respectively. The nature of the bias conditions applied to the word line and to the cell bit lines BL and BL will determine whether a read operation or a write operation is to be performed with respect to the accessed cell.
Referring back to FIG. 1, word line 1 is utilized to access a selected memory cell 40 in the row 100. The complementary data stored in SRAM cell 40 is placed on complementary bit lines BL0 and BL0 by enabling the internal cell pass gate transistors associated with cell 40. The data from the bit lines BL0 and BL0 is transferred to an associated transfer bus (i.e. complementary transfer buses TBUS1 and TBUS1) 11 by enabling associated column select transistor pair 19 utilizing select signal SEL1. Select signal SEL1 is provided by a column decoder 15 in response to a corresponding four bit address (i.e. bits A0, /A0, A1 and /A1) provided to the column decoder 15 on address bus 6.
As further shown in FIG. 1, transfer bus (TBUS1/TBUS1) 11 is connected to receive data from four individual SRAM cells. Each of these cells is controlled by a different column select transistor pair (i.e. transistor pairs 19, 23, 27, and 31) in each of four 4-cell groups that are selected by the four column decoders (i.e. column decoders 15, 16, 17 and 18, respectively) associated with the row 100.
That is, the circuit shown in FIG. 1 has a "by-four" architecture wherein a selected group 45 of four SRAM cells (i.e., cells 40, 41, 42 and 43) is selected by the column decoder 15. The data from these four cells is transferred onto four corresponding transfer buses (i.e., complementary transfer bus pairs 11, 12, 13 and 14). The data on each of these transfer buses is amplified by a corresponding sense amplifier and provided to a corresponding input/output pin (i.e. I/O pins 7, 8, 9 and 10, respectively).
As shown in FIG. 1, in order to service each of the four groups of cells, each of the transfer buses must physically travel the entire length of the word line 1. Furthermore, the four column decoders are placed four bits, i.e. four cells, apart along the length of the word line. Thus, the length of the transfer bus for each bit is proportional to the length of the word line, creating additional capacitance on the transfer bus. This added capacitance is seen directly by the memory cells attached to the transfer bus through the column select transistors, thereby slowing memory access time.
It would, therefore, be highly desirable to have available a high density memory array architecture in which the transfer bus capacitance seen by individual memory cells is reduced, but with no area penalty.